1. Field of the Invention
The present invention relates to a semiconductor device and test method therefor, and is applied to tests for, e.g., a memory equipped with a redundancy circuit and a memory-embedded microcomputer.
2. Description of the Related Art
Highly integrated semiconductor devices require a manufacturing process which adopts more advanced micropatterning. The efficiency percentage, i.e., yield of products sensitively depends on the presence of dust and dirt in the manufacturing process, variations in process, and the like. The percentage of complete nondefectives in which all bits are nondefective is naturally low for highly integrated memories. Under such a circumstance, the yield must be increased by a technique of preparing redundancy spare cells in addition to memory cells of a necessary capacity, and replacing a defective memory cell with a spare cell to repair the defective memory cell (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2000-57795).
However, the cost of tests is high and occupies a large portion of the unit cost of a memory equipped with a redundancy circuit or a memory-embedded microcomputer. This is because the above-mentioned technique requires not only a time taken to test the function and reliability of a memory cell but also a function test for checking the function of the entire memory area including a defective cell repair redundancy circuit and a test for checking whether a defective cell can be repaired.
In general, after the manufacturing process of a memory ends, a function test is conducted on the initial stage. If a defective cell is detected, it is repaired by a redundancy circuit, and then the process advances to the next test step. The function test on the initial stage is done following, e.g., the next procedures.
Write/read and erase/read are executed at a high temperature for respective chips of a wafer having undergone the manufacturing process, and a fail bit map is created by a memory tester. The presence/absence of defective cells is determined on the basis of the fail bit map. If no defective cell exists, the chip is determined to be nondefective, and the process normally ends. If a defective cell exists, whether the repair is possible is determined on the basis of the fail bit map. If it is determined on this stage that the repair is impossible, the chip is determined to be a defective chip, and the test ends. If the repair is determined to be possible, the defective chip is repaired by replacing with a spare cell a defective cell at an address stored on the fail bit map. The function test is conducted again to check whether the replaced spare cell functions normally.
In the function retest, write/read and erase/read are executed at a high temperature in the above-described way, and a fail bit map is created by the memory tester. The presence/absence of defective cells is determined on the basis of the fail bit map. If no defective cell exists, the chip is determined to be nondefective, and the process normally ends. If a defective cell exists, whether the repair is possible is determined on the basis of the fail bit map. If the repair is determined to be impossible, the chip is determined to be a defective chip, and the test ends. If the repair is determined to be possible, the defective chip is repaired by replacing with a spare cell a defective cell at an address stored on the fail bit map. The function test is then conducted again.
This operation is repeated for memory cells at all addresses as far as spare cells remain. The chip quality can be determined, and a defective cell can be repaired by replacing it with a spare cell.
At this time, the problem lies in the memory function test and the redundancy replacement time. This test poses problems (1) to (4) because a fail bit map is created using the memory tester and the function test and redundancy replacement are executed on the basis of the fail bit map.
(1) In order to create a fail bit map using the memory tester, data must be written from the memory tester to a memory (chip) and read out from the chip to the memory tester. A long time is taken for data transfer between the chip and the tester. For a large-capacity memory, a large amount of data must be transferred from the tester and written, and a large amount of data must be read out and transferred to the tester. A long time is taken for the data transfer.
(2) The address width of a memory and its data width capable of read/write at once are determined by chip specifications, and the input/output data amount is limited. For example, to input/output 32-bit data to/from a chip capable of 8-bit external input/output, the data must be divided into four and separately read/written. As a result, the data read/write time becomes long.
(3) Creation of a fail bit map needs an expensive memory tester and complicated processes.
(4) A dedicated program is necessary for recognizing the address of a defective cell subjected to redundancy replacement on the basis of the fail bit map created by the memory tester.
As described above, the conventional semiconductor device and test method therefor suffer a long test time and high test cost. The rise in test cost is reflected in the cost of the semiconductor device, and increases the unit cost of the product.